Level 6 — Module I — Computer Architecture — Jul/Aug 2026
Module I • Level 6 • July/August 2026 • Written assessment
Work through each question before checking the answer. These revision answers are prepared for learners; they are not an official marking scheme.
Question 1
Give two differences between computer architecture and organisation.
Answer
| Architecture | Organisation |
|---|---|
| Programmer-visible features, such as instruction set and addressing modes | Internal implementation, such as control signals, datapaths and memory connections |
| Defines the behaviour and facilities software can use | Defines how hardware is arranged to implement that behaviour |
Question 2
List four ICT concepts used in computer systems.
Answer
- Data representation and encoding.
- Information processing.
- Data storage and retrieval.
- Communication and networking.
Question 3
Identify four hardware components.
Answer
- Processor (CPU).
- Main memory (RAM).
- Storage device such as an SSD.
- Motherboard with buses and interfaces.
Question 4
State four CPU functions.
Answer
- Fetches program instructions.
- Decodes instructions.
- Executes arithmetic and logical operations.
- Coordinates control flow and data transfers with memory and I/O.
Question 5
List four CPU register types.
Answer
- Program counter (PC).
- Instruction register (IR).
- Memory address register (MAR).
- Memory data/buffer register (MDR/MBR).
Question 6
Give four stages of the instruction cycle.
Answer
- Fetch the instruction from the address in the program counter.
- Decode the instruction and identify the operands.
- Execute the operation.
- Write/store the result and update processor state for the next instruction.
Question 7
List four computer memory types.
Answer
- Registers.
- Cache.
- RAM.
- ROM/non-volatile firmware memory.
Question 8
Identify three storage technologies.
Answer
- Magnetic storage such as HDDs.
- Solid-state/flash storage such as SSDs.
- Optical storage such as CDs, DVDs and Blu-ray discs.
Question 9
State three I/O transfer modes.
Answer
- Programmed/polled I/O.
- Interrupt-driven I/O.
- Direct memory access (DMA).
Question 10
Give four I/O devices and their basic connection requirements.
Answer
| Device | Requirements |
|---|---|
| Keyboard | Supported USB port or paired wireless interface; suitable OS driver |
| Mouse | Supported USB port or paired wireless interface; suitable OS driver |
| Monitor | Compatible HDMI/DisplayPort or other display connection plus power |
| Printer | Supported USB/network connection, power, and compatible printer driver |
Question 11
State two bus-interface functions.
Answer
- Provides pathways for data, address and control signals between components.
- Coordinates and arbitrates transfers so compatible devices communicate at the required timing/protocol.
Question 12
Identify two CPU specifications.
Answer
- Architecture/instruction set and supported word size.
- Core/thread count and clock frequency; these do not alone determine application performance.
Question 13
Explain two memory organisations, three cache benefits, two memory performance roles, and compare primary/secondary memory by size, speed and usage.
Answer
- Von Neumann organisation uses a shared address space/path for program instructions and data.
- Harvard organisation separates instruction and data memories/buses, permitting simultaneous access; practical processors can use modified Harvard designs.
- Cache reduces average access latency for frequently reused data/instructions.
- It exploits spatial locality by retaining nearby items in a cache line.
- It reduces repeated main-memory transfers and CPU stalls.
- Adequate main memory holds the active working set and reduces slow paging.
- Memory latency/bandwidth affects how quickly the CPU and devices obtain data.
| Aspect | Primary memory | Secondary storage |
|---|---|---|
| Size | Usually smaller | Usually larger |
| Speed | Typically faster; CPU-addressable working storage | Usually slower; data must be brought into working memory |
| Usage | Active instructions and data (RAM/cache) | Persistent programs, documents and backups (SSD/HDD) |
Question 14
Compare programmed I/O and DMA; give three DMA advantages, two preferred uses and three efficiency improvements.
Answer
| Aspect | Programmed I/O | DMA |
|---|---|---|
| Transfer work | CPU executes instructions for each transfer | Controller transfers a block after CPU setup |
| CPU use | Often polls and remains occupied moving data | CPU can perform other work; completion is normally reported by interrupt |
- Reduces CPU overhead for large transfers.
- Allows greater overlap of computation with I/O.
- Can increase block-transfer throughput.
- Moving disk/SSD blocks to or from memory.
- High-volume network, audio or video data transfers.
- Fewer per-byte instructions leave more CPU time for application work.
- Block/burst transfers use the bus efficiently.
- Fewer completion notifications than per-item CPU transfers can reduce overhead. DMA still needs arbitration and cache-coherency management where applicable.
Question 15
Convert 25₁₀ to binary and 1A₁₆ to decimal; add 1011₂ and 0101₂; explain four IEEE 754 representation features.
Answer
Step-by-step calculation
- 25 ÷ 2 gives quotient/remainder pairs: 12 r1, 6 r0, 3 r0, 1 r1, 0 r1.
- Read remainders bottom to top: 25₁₀ = 11001₂.
- 1A₁₆ = 1×16 + 10 = 26₁₀.
- 1011₂ + 0101₂ = 11 + 5 = 16 = 10000₂; the carry creates a fifth bit.
- A sign field indicates positive or negative values.
- A biased exponent represents the scale; binary32 uses eight exponent bits with bias 127 for normal numbers.
- A significand/fraction represents precision; binary32 has 23 stored fraction bits with an implicit leading 1 for normal values.
- Special encodings support signed zero, subnormal numbers, infinities and NaNs, with defined rounding behaviour.
Question 16
Explain AND, OR and NOT; justify all input cases of a two-input AND gate, give its truth table and a real-life application.
Answer
- AND produces 1 only when every input is 1.
- OR produces 1 when at least one input is 1.
- NOT inverts a single bit: 0 becomes 1 and 1 becomes 0.
| A | B | A AND B | Reason |
|---|---|---|---|
| 0 | 0 | 0 | Neither condition is met |
| 0 | 1 | 0 | A is false |
| 1 | 0 | 0 | B is false |
| 1 | 1 | 1 | Both conditions are true |
The question’s “three outputs” wording is imprecise: a two-input gate has four input combinations and two possible output values. For a machine interlock, enable = guard closed AND start requested; both conditions must be true.